Altera Stratix GX User Manual

[Page 1] Altera Stratix GX

101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Stratix GX Transceiver User Guide UG-STXGX-3.0 P25-10021-02 ...

[Page 2] Altera Stratix GX

Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des- ignations, and all other words and logos that are identified as trademarks and/or service marks are,...

[Page 3] Altera Stratix GX

Altera Corporation iii Contents About This User Guide ............................................................................ vii How to Contact Altera ..........................................................................................

[Page 4] Altera Stratix GX

iv Altera Corporation Contents Stratix GX Transceiver User Guide Byte Serializer ................................................................................................................................. 3–17 8B/10B Encoder ................

[Page 5] Altera Stratix GX

Altera Corporation v Contents Contents Chapter 6. GigE Mode Introduction ............................................................................................................................................ 6–1 Word Aligner ..............

[Page 6] Altera Stratix GX

vi Altera Corporation Contents Stratix GX Transceiver User Guide Chapter 9. Reset Control & Power Down Introduction .................................................................................................................................

[Page 7] Altera Stratix GX

Altera Corporation vii Preliminary About This User Guide How to Contact Altera For the most up-to-date information about Altera ® products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to w...

[Page 8] Altera Stratix GX

viii Altera Corporation Preliminary Typographic Conventions Stratix GX Transceiver User Guide Typographic Conventions This document uses the typographic conventions shown below. Visual Cue Meaning Bold Type with Initial Capital Letters Command na...

[Page 9] Altera Stratix GX

Altera Corporation 1–1 January 2005 1. Introduction Introduction Stratix ® GX devices combine highly advanced 3.1875-gigabit-per-second (Gbps) four-channel gigabit transceiver blocks with one of the industry’s most advanced FPGA archit...

[Page 10] Altera Stratix GX

1–2 Altera Corporation Stratix GX Transceiver User Guide January 2005 Transceiver Block Architecture Transceiver Block Architecture Figure 1–1 shows a block diagram of the gigabit transceiver block (GXB). You can bypass various modules if d...

[Page 11] Altera Stratix GX

Altera Corporation 1–3 January 2005 Stratix GX Transceiver User Guide Introduction Transmitter & Receiver PLLs Each gigabit transceiver block contains one dedicated transmitter PLL and four dedicated receiver PLLs. These PLLs provide clock...

[Page 12] Altera Stratix GX

1–4 Altera Corporation Stratix GX Transceiver User Guide January 2005 Transceiver Block Architecture Transmitter & Receiver Phase Compensation FIFO Buffer The transmitter and receiver data path has a dedicated phase compensation FIFO buffer...

[Page 13] Altera Stratix GX

Altera Corporation 1–5 January 2005 Stratix GX Transceiver User Guide Introduction Channel Aligner An embedded channel aligner aligns byte boundaries across multiple channels and synchronizes the data entering the logic array from the gigabit...

[Page 14] Altera Stratix GX

1–6 Altera Corporation Stratix GX Transceiver User Guide January 2005 Modes of Operation Figure 1–2. Block Diagram of a Duplex Channel Configured in Basic Mode SONET Mode SONET mode lets you to select a subset of the transceiver blocks to per...

[Page 15] Altera Stratix GX

Altera Corporation 1–7 January 2005 Stratix GX Transceiver User Guide Introduction Figure 1–3. Block Diagram of a Duplex Channel Configured in SONET Mode XAUI Mode Stratix GX transceivers contain embedded macros dedicated to supporting the X...

[Page 16] Altera Stratix GX

1–8 Altera Corporation Stratix GX Transceiver User Guide January 2005 Modes of Operation Figure 1–4. Block Diagram of a Duplex Channel Configured in XAUI Mode GigE Mode Stratix GX devices in GigE mode can use the 8B/10B encoder/decoder, rate ...

[Page 17] Altera Stratix GX

Altera Corporation 1–9 January 2005 Stratix GX Transceiver User Guide Introduction Figure 1–5. Block Diagram of a Duplex Channel Configured in GigE Mode Loopback There are three different loopback modes to use in the gigabit transceiver bloc...

[Page 18] Altera Stratix GX

1–10 Altera Corporation Stratix GX Transceiver User Guide January 2005 Modes of Operation ...

[Page 19] Altera Stratix GX

Altera Corporation 2–1 January 2005 2. Stratix GX Analog Description Introduction This chapter describes how to serialize the parallel data for transmission and convert received data into parallel data. Data transmission and reception is ...

[Page 20] Altera Stratix GX

2–2 Altera Corporation Stratix GX Transceiver User Guide January 2005 Transmitter Analog Figure 2–1. Block Diagram Analog Components Transmitter Analog This section describes the transmitter buffer, the transmitter PLL, and the serializer. F...

[Page 21] Altera Stratix GX

Altera Corporation 2–3 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description Programmable Voltage Output Differential (V OD ) Stratix GX transceivers let you customize the differential output voltage (V OD ) to handle di...

[Page 22] Altera Stratix GX

2–4 Altera Corporation Stratix GX Transceiver User Guide January 2005 Transmitter Analog You can set the differential V OD values statically during configuration or dynamically adjust them in user mode. You select the static V OD value throu...

[Page 23] Altera Stratix GX

Altera Corporation 2–5 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description As with the V OD settings, you can set the pre-emphasis settings statically during configuration or adjust them dynamically in user mode. You ...

[Page 24] Altera Stratix GX

2–6 Altera Corporation Stratix GX Transceiver User Guide January 2005 Transmitter Analog Figure 2–4. Transmitter PLL Block Diagram Table 2–2 lists some of the transmitter PLL specifications. Clock Synthesis The maximum input frequency of the...

[Page 25] Altera Stratix GX

Altera Corporation 2–7 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description If the reference clock exceeds 325 MHz, the clock must be fed by the dedicated local reference clock pin, REFCLKB. By default, the Quartus II ...

[Page 26] Altera Stratix GX

2–8 Altera Corporation Stratix GX Transceiver User Guide January 2005 Transmitter Analog A high-bandwidth setting provides a faster lock time and tracks more jitter on the input clock source which passes it through the PLL. This helps reject n...

[Page 27] Altera Stratix GX

Altera Corporation 2–9 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description Figure 2–6. Serializer Bit Order Receiver Analog This section describes the receiver input buffer, the receiver PLL, the clock recovery unit...

[Page 28] Altera Stratix GX

2–10 Altera Corporation Stratix GX Transceiver User Guide January 2005 Receiver Analog Figure 2–8. Receiver Input Buffer Programmable Receiver Termination The Stratix GX receiver buffer includes programmable on-chip differential termination o...

[Page 29] Altera Stratix GX

Altera Corporation 2–11 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description If external termination is used, the receiver must be externally terminated and biased to 1.1 V. Figure 2–9 shows an example of an external ...

[Page 30] Altera Stratix GX

2–12 Altera Corporation Stratix GX Transceiver User Guide January 2005 Receiver Analog This variation in frequency response yields data-dependant jitter and other ISI effects. By applying equalization, the low frequency components are attenuat...

[Page 31] Altera Stratix GX

Altera Corporation 2–13 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description The receiver PLL contains an optional loss-of-lock indicator signal (rx_locked) that indicates when the receiver PLL is not locked to the ref...

[Page 32] Altera Stratix GX

2–14 Altera Corporation Stratix GX Transceiver User Guide January 2005 Receiver Analog where the reference clock signal is divided by 2, yielding a 311 MHz clock at the PFD. This 311-MHz reference clock is then multiplied by a factor of 8 to a...

[Page 33] Altera Stratix GX

Altera Corporation 2–15 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description Table 2–5 lists the possible multiplication values as a function of the reference clock source to the receiver PLL. Table 2–5 assumes that...

[Page 34] Altera Stratix GX

2–16 Altera Corporation Stratix GX Transceiver User Guide January 2005 Receiver Analog Valid receiver bandwidth settings are low, medium, and high. The –3-dB frequencies for these settings vary due to the non-linear nature and data dependenc...

[Page 35] Altera Stratix GX

Altera Corporation 2–17 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description During the lock-to-reference mode, the frequency detector determines whether the reference clock to the receiver PLL and the VCO output are w...

[Page 36] Altera Stratix GX

2–18 Altera Corporation Stratix GX Transceiver User Guide January 2005 Receiver Analog or not the CRU is ready. When both signals are asserted, the rx_locktodata[] signal takes precedence over the rx_locktorefclk[] signal. You might want to ha...

[Page 37] Altera Stratix GX

Altera Corporation 2–19 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description If the data width is 8 or 16, set the legal run length threshold values within the range of 4 to 128 UI in multiples of four. If the data widt...

[Page 38] Altera Stratix GX

2–20 Altera Corporation Stratix GX Transceiver User Guide January 2005 MegaWizard Analog Features Figure 2–12. Deserializer Bit Order MegaWizard Analog Features This section describes the analog options for the instantiation of the altgxb me...

[Page 39] Altera Stratix GX

Altera Corporation 2–21 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description Figure 2–13. MegaWizard Plug-In Manager - ALTGXB (Page 1 of 7) - General (1) Notes (1)–(4) Notes to Figure 2–13: (1) Option available in ...

[Page 40] Altera Stratix GX

2–22 Altera Corporation Stratix GX Transceiver User Guide January 2005 MegaWizard Analog Features Figure 2–14. MegaWizard Plug-In Manager - ALTGXB (Page 2 of 7) - General (2) Notes (1), (2) Notes to Figure 2–14: (1) For information, refer to...

[Page 41] Altera Stratix GX

Altera Corporation 2–23 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description Figure 2–15. MegaWizard Plug-In Manager - ALTGXB (Page 3 of 7) - Receiver (1) Note (1) Note to Figure 2–15: (1) Enable run length violation...

[Page 42] Altera Stratix GX

2–24 Altera Corporation Stratix GX Transceiver User Guide January 2005 MegaWizard Analog Features Figure 2–16. MegaWizard Plug-In Manager - ALTGXB (Page 4 of 7) - Receiver (2) Notes (1)–(3) Notes to Figure 2–16: (1) Stratix GX to Stratix G...

[Page 43] Altera Stratix GX

Altera Corporation 2–25 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description Figure 2–17. MegaWizard Plug-In Manager - ALTGXB (Page 5 of 7) - Receiver (3) Notes (1)–(3) Notes to Figure 2–17: (1) Optional input sign...

[Page 44] Altera Stratix GX

2–26 Altera Corporation Stratix GX Transceiver User Guide January 2005 MegaWizard Analog Features Figure 2–18. MegaWizard Plug-In Manager - ALTGXB (Page 6 of 7) - Transmitter Notes (1), (2) Notes to Figure 2–18: (1) The Use V OD control sig...

[Page 45] Altera Stratix GX

Altera Corporation 2–27 January 2005 Stratix GX Transceiver User Guide Stratix GX Analog Description Figure 2–19. MegaWizard Plug-In Manager - ALTGXB (Page 7of 7) - Summary ...

[Page 46] Altera Stratix GX

2–28 Altera Corporation Stratix GX Transceiver User Guide January 2005 MegaWizard Analog Features ...

[Page 47] Altera Stratix GX

Altera Corporation 3–1 January 2005 3. Basic Mode Introduction The basic mode of the Stratix ® GX device includes the following features: ■ Serial data rate range from 500 Mbps to 3.1875 Gbps ■ Input reference clock range from 25 to 65...

[Page 48] Altera Stratix GX

3–2 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Receiver Architecture Figure 3–1. Block Diagram of a Duplex Channel Configured in Basic Mode Basic Mode Receiver Architecture Figure 3–2 shows a block diagram...

[Page 49] Altera Stratix GX

Altera Corporation 3–3 January 2005 Stratix GX Transceiver User Guide Basic Mode word alignment circuit that is used in conjunction with the pattern detector to align the word boundary of the re-timed data to a specified comma. In basic mode,...

[Page 50] Altera Stratix GX

3–4 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Receiver Architecture A 10-bit pattern, 7-bit pattern, or 16-bit pattern can be programmed for the pattern detector to recognize. Refer to the section “Basic Mod...

[Page 51] Altera Stratix GX

Altera Corporation 3–5 January 2005 Stratix GX Transceiver User Guide Basic Mode Manual Alignment Modes The Stratix GX device supports manual alignment in 10-bit, 16-bit, and bit-slipping modes. Manual 10-Bit Alignment Mode You can configure t...

[Page 52] Altera Stratix GX

3–6 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Receiver Architecture Figure 3–5 shows an example of how the word aligner signals interact in 10-bit alignment mode. For this example, a /K28.5/ (10'b00111...

[Page 53] Altera Stratix GX

Altera Corporation 3–7 January 2005 Stratix GX Transceiver User Guide Basic Mode The byte boundary is locked after the first comma is detected and aligned after the rising edge of the rx_enacdet[] signal. If the byte boundary changes, the rx_...

[Page 54] Altera Stratix GX

3–8 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Receiver Architecture deasserted and the A1 pattern is present on the rx_word_align_out port. At time n+6, the A2 pattern is present on the rx_word_align_out port...

[Page 55] Altera Stratix GX

Altera Corporation 3–9 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–7. Example of How the Word Aligner Symbols Interact in Manual Bitslip Mode 8B/10B Decoder The 8B/10B decoder is part of the Stratix GX transceiver block...

[Page 56] Altera Stratix GX

3–10 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Receiver Architecture Figure 3–8. 10-Bit to 8-Bit Conversion Reset The rxdigitalreset signal governs the reset condition of the 8B/10B decoder. In reset, the di...

[Page 57] Altera Stratix GX

Altera Corporation 3–11 January 2005 Stratix GX Transceiver User Guide Basic Mode Disparity Error Detector The 8B/10B decoder can detect disparity errors based on which 10-bit code it received. The disparity error is indicated at the optional ...

[Page 58] Altera Stratix GX

3–12 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Receiver Architecture Figure 3–9. Disparity Error Control Detect The 8B/10B can differentiate between data and control codes via the rx_ctrldetect port. This po...

[Page 59] Altera Stratix GX

Altera Corporation 3–13 January 2005 Stratix GX Transceiver User Guide Basic Mode Byte Deserializer The byte deserializer module further reduces the speed at which the FPGA logic array must run in order to meet performance. If the input is 10...

[Page 60] Altera Stratix GX

3–14 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Receiver Architecture Figure 3–11. Receiver Byte Deserialzer in 10/20-Bit Mode With Alignment Pattern in MSB Figure 3–12 demonstrates the alternate case of the...

[Page 61] Altera Stratix GX

Altera Corporation 3–15 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–13. Receiver Byte Deserialzer Data Recovery in Logic Array Receiver Phase Compensation FIFO Buffer The receiver phase compensation FIFO buffer is locat...

[Page 62] Altera Stratix GX

3–16 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Transmitter Architecture In basic mode, if the RX_CLKOUT port is not selected for use, the read clock is clocked by RX_CORECLK, which is fed by RX_CLKOUT. An FPGA...

[Page 63] Altera Stratix GX

Altera Corporation 3–17 January 2005 Stratix GX Transceiver User Guide Basic Mode If the TX_CORECLK is not selected as an optional input transmitter port, TX_CORECLK is fed by CORECLK_OUT. This connection occurs using the logic array routing....

[Page 64] Altera Stratix GX

3–18 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Transmitter Architecture For additional information regarding the 8B/10B code itself, refer to Appendix A, Data & Control Codes. The 8B/10B encoder translates...

[Page 65] Altera Stratix GX

Altera Corporation 3–19 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–17 shows the reset behavior of the 8B/10B encoder. When in reset (txdigitalreset is high), a K28.5- (K28.5 10-bit code from the RD- column) is sent c...

[Page 66] Altera Stratix GX

3–20 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Clocking An example would be the invalid code encoding of a K24.1 (data = 8'h38 + tx_ctrlenable = 1'b1). Depending on the current running disparity, th...

[Page 67] Altera Stratix GX

Altera Corporation 3–21 January 2005 Stratix GX Transceiver User Guide Basic Mode On the transmitter channel the output of the transmitter PLL, coreclk_out, is sent into the logic array and also loops back to clock the write side of the trans...

[Page 68] Altera Stratix GX

3–22 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Clocking This configuration has an independent rx_cruclk that feeds the receiver PLL reference clock. This input clock port is only available when the receiver P...

[Page 69] Altera Stratix GX

Altera Corporation 3–23 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–21. altgxb in Basic Mode With rx_coreclk & tx_coreclk Enabled Table 3–3 displays a list of the input and output clock ports available in basic m...

[Page 70] Altera Stratix GX

3–24 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Clocking Basic Mode Inter-Transceiver Block Clocking This section describes guidelines for using transceiver interface clocking between the device logic array and...

[Page 71] Altera Stratix GX

Altera Corporation 3–25 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–22. Example of a Multi-Transceiver Block Device to Transmitter Interface Clocking Scheme in Basic Mode When TX_CORECLK is not enabled, the Quartus II ...

[Page 72] Altera Stratix GX

3–26 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Clocking Another inter-transceiver block consideration is the selection of the dedicated REFCLKB pin. Stratix GX channels are arranged in banks of four, or trans...

[Page 73] Altera Stratix GX

Altera Corporation 3–27 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–23. Inter-Transceiver Line Connections for EP1SGX25 Device 16 IQ0 IQ1 IQ2 Transceiver Block 0 IQ0 IQ1 Global Clocks, I/O Bus, General Routing Global Cl...

[Page 74] Altera Stratix GX

3–28 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode Clocking Figure 3–24 shows the transceiver routing with respect to inter- transceiver lines for the EP1SGX40G Device. This device has an extra transceiver block...

[Page 75] Altera Stratix GX

Altera Corporation 3–29 January 2005 Stratix GX Transceiver User Guide Basic Mode Basic Mode MegaWizard Plug-In Altera recommends that the Stratix GX transceiver block be instantiated and parameterized through the altgxb megafunction in the ...

[Page 76] Altera Stratix GX

3–30 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode MegaWizard Plug-In Figure 3–25. MegaWizard Plug-In Manager - ALTGXB (Page 3 of 9) - General (1) Notes (1)–(5) Notes to Figure 3–25: (1) Basic protocol mode s...

[Page 77] Altera Stratix GX

Altera Corporation 3–31 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–26. MegaWizard Plug-In Manager - ALTGXB (Page 4 of 9) - General (2) Notes (1), (2) Notes to Figure 3–26: (1) For more information, refer to the Loopb...

[Page 78] Altera Stratix GX

3–32 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode MegaWizard Plug-In Figure 3–27. MegaWizard Plug-In Manager - ALTGXB (Page 5 of 9) - Receiver (1) Notes (1), (2) Notes to Figure 3–27: (1) You can enable or dis...

[Page 79] Altera Stratix GX

Altera Corporation 3–33 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–28. MegaWizard Plug-In Manager - ALTGXB (Page 6 of 9) - Receiver (2) Notes (1), (2) Notes to Figure 3–28: (1) For more information, refer to the Stra...

[Page 80] Altera Stratix GX

3–34 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode MegaWizard Plug-In Figure 3–29. MegaWizard Plug-In Manager - ALTGXB (Page 7 of 9) - Receiver (3) Notes (1)–(5) Notes to Figure 3–29: (1) For more information...

[Page 81] Altera Stratix GX

Altera Corporation 3–35 January 2005 Stratix GX Transceiver User Guide Basic Mode Figure 3–30. MegaWizard Plug-In Manager - ALTGXB (Page 8 of 9) - Transmitter Note (1) Notes to Figure 3–30: (1) For more information, refer to the Stratix GX ...

[Page 82] Altera Stratix GX

3–36 Altera Corporation Stratix GX Transceiver User Guide January 2005 Basic Mode MegaWizard Plug-In Figure 3–31. MegaWizard Plug-In Manager - ALTGXB (Page 9 of 9) - Summary ...

[Page 83] Altera Stratix GX

Altera Corporation 4–1 January 2005 4. SONET Mode Introduction One of the most common serial backplanes in the communications or telecom area is the SONET/SDH interface. For SONET/SDH applications the synchronous transport signal STS-48 a...

[Page 84] Altera Stratix GX

4–2 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Receiver Architecture Figure 4–1. Block Diagram of Transceiver Channel Configured in SONET Mode SONET Mode Receiver Architecture Figure 4–2 shows the digital ...

[Page 85] Altera Stratix GX

Altera Corporation 4–3 January 2005 Stratix GX Transceiver User Guide SONET Mode embedded word alignment circuit to use in conjunction with the pattern detector to align the word boundary of the re-timed data to a specified comma. In SONET mo...

[Page 86] Altera Stratix GX

4–4 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Receiver Architecture Manual SONET Alignment Mode (2 Consecutive 8-bit Characters (A1A2) or 4 Consecutive 8-bit Characters (A1A1A2A2) The 2 consecutive 8-bit chara...

[Page 87] Altera Stratix GX

Altera Corporation 4–5 January 2005 Stratix GX Transceiver User Guide SONET Mode In SONET mode, the byte boundary is locked after the first comma is detected, and the boundary is aligned after the rising edge of the rx_enacdet[] signal. If th...

[Page 88] Altera Stratix GX

4–6 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Receiver Architecture Figure 4–4. Word Aligner Symbols Interacting in SONET A1A2 Manual Alignment Mode The rx_a1a2size signal is held low. This low signal sets th...

[Page 89] Altera Stratix GX

Altera Corporation 4–7 January 2005 Stratix GX Transceiver User Guide SONET Mode comma, the rx_patterndetect[] signal is asserted for one clock cycle. You must implement the logic in the device logic array to control the bit-slip circuitry. ...

[Page 90] Altera Stratix GX

4–8 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Receiver Architecture Byte Deserializer The byte deserializer module further reduces the speed that the FPGA logic array must achieve in order to meet performance....

[Page 91] Altera Stratix GX

Altera Corporation 4–9 January 2005 Stratix GX Transceiver User Guide SONET Mode Figure 4–7 demonstrates the alternate case of the finishing alignment pattern found in the LSB of the 16-bit output. Correspondingly patterndetect[0] goes high...

[Page 92] Altera Stratix GX

4–10 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Receiver Architecture Figure 4–8. Receiver Byte Deserializer Data Recovery in Logic Array Receiver Phase Compensation FIFO Module The receiver phase compensation...

[Page 93] Altera Stratix GX

Altera Corporation 4–11 January 2005 Stratix GX Transceiver User Guide SONET Mode for the read clock. Refer to “SONET Mode Channel Clocking” on page 4–12 or the block diagram in the MegaWizard Plug-In Manager for more information on the...

[Page 94] Altera Stratix GX

4–12 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Clocking The Transmitter Phase Compensation FIFO module is always used and cannot be bypassed. The input to the Transmitter Phase Compensation FIFO module is the...

[Page 95] Altera Stratix GX

Altera Corporation 4–13 January 2005 Stratix GX Transceiver User Guide SONET Mode Figure 4–11. Default Configuration of altgxb in SONET Mode In Figure 4–11, the altgxb megafunction is configured so that the train receiver PLL with transmit...

[Page 96] Altera Stratix GX

4–14 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Clocking frequency detector of the receiver PLL. For more information on this feature, refer to the Stratix GX Analog Description chapter. This configuration is ...

[Page 97] Altera Stratix GX

Altera Corporation 4–15 January 2005 Stratix GX Transceiver User Guide SONET Mode The coreclk_out is the output from the transmitter PLL. A coreclk_out is available for each transceiver block that is used. Altera ® recommends clocking the l...

[Page 98] Altera Stratix GX

4–16 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Clocking Figure 4–13. altgxb in SONET Mode With rx_coreclk & tx_coreclk Enabled For reference, the various input and output clock ports are listed in Table ...

[Page 99] Altera Stratix GX

Altera Corporation 4–17 January 2005 Stratix GX Transceiver User Guide SONET Mode SONET Mode Inter-Transceiver Block Clocking This section provides guidelines for using transceiver interface clocking between the FPGA logic array and transceive...

[Page 100] Altera Stratix GX

4–18 Altera Corporation Stratix GX Transceiver User Guide January 2005 SONET Mode Clocking One of the clocking interfaces to consider while designing with Stratix GX devices is the transceiver-to-FPGA interface. This clocking scheme is further...