Cypress Semiconductor CY7C1217H Specification Sheet

[Page 1] Cypress Semiconductor CY7C1217H

CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05670 Rev. *B Revised July 6, 2006 Features • 32K x 36 common I/O • 3.3V core...

[Page 2] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 2 of 16 Logic Block Diagram ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQ s DQP A DQP B DQP C DQP D A ...

[Page 3] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 3 of 16 Pin Configuration 100-Pin TQFP A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/9M A A A A A NC/4M DQP B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ...

[Page 4] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 4 of 16 Pin Descriptions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 32K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active ...

[Page 5] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 5 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device). The...

[Page 6] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 6 of 16 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 40 mA t ZZS Device operation to ZZ ZZ > V DD – ...

[Page 7] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 7 of 16 Truth Table for Read/Write [2, 3] Function GW BWE BW D BW C BW B BW A Read HHXXXX Read HLHHHH Write Byte (A, DQP A ) HLHHHL Write Byte (B, DQP B )HLHHLH Write Bytes (B, A, DQP A , DQP B )HLHHLL Writ...

[Page 8] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................–65°C to + 150°C Ambient Temperature with P...

[Page 9] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 9 of 16 Capacitance [9] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V. V DDQ = 2.5V 5pF C CLK Clock Input Capacitance 5 pF C I...

[Page 10] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 10 of 16 Switching Characteristics Over the Operating Range [10, 11] Parameter Description 133 MHz 100 MHz UnitMin. Max. Min. Max. t POWER V DD (Typical) to the First Access [12] 11ms Clock t CYC Clock Cyc...

[Page 11] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 11 of 16 Timing Diagrams Read Cycle Timing [16] Note: 16. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t...

[Page 12] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 12 of 16 Write Cycle Timing [16, 17] Note: 17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS ...

[Page 13] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 13 of 16 Read/Write Timing [16, 18, 19] Notes: 18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC, or ADV cycle is performed. 19. GW is HIGH. Timing Diagrams (continued...

[Page 14] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 14 of 16 ZZ Mode Timing [20, 21] Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in High-Z wh...

[Page 15] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 15 of 16 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any cir...

[Page 16] Cypress Semiconductor CY7C1217H

CY7C1217H Document #: 38-05670 Rev. *B Page 16 of 16 Document History Page Document Title: CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM Document Number: 38-05670 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 345879 See ECN P...