Cypress Semiconductor CY7C1316BV18 Specification Sheet

[Page 1] Cypress Semiconductor CY7C1316BV18

18-Mbit DDR-II SRAM 2-Word Burst Architecture CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-05621 Rev. *D Revised June...

[Page 2] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 2 of 31 Logic Block Diagram (CY7C1316BV18) Logic Block Diagram (CY7C1916BV18) Write Reg Write Reg CLK A (19:0) Gen. K K Control Logic Address Register Read...

[Page 3] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 3 of 31 Logic Block Diagram (CY7C1318BV18) Logic Block Diagram (CY7C1320BV18) Write Reg Write Reg CLK A (19:0) Gen. K K Control Logic Address Register Read...

[Page 4] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 4 of 31 Pin Configuration The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.4 ...

[Page 5] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 5 of 31 CY7C1318BV18 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W BWS 1 K NC/144M LD A NC/36M CQ B NC DQ9 NC A NC/288M K BWS 0 ANCNCDQ8 C NC NC NC V ...

[Page 6] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 6 of 31 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input Output- Synchronous Data Input Output Signals. Inputs are sampled on the rising edge of ...

[Page 7] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 7 of 31 CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the DDR...

[Page 8] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 8 of 31 Functional Overview The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are synchronous pipelined Burst SRAMs equipped with a DDR interfa...

[Page 9] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 9 of 31 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V SS to enable the SRAM to adjust its output ...

[Page 10] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 10 of 31 Truth Table The truth table for the CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ D...

[Page 11] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 11 of 31 Write Cycle Descriptions The write cycle description table for CY7C1916BV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the data portion ...

[Page 12] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 12 of 31 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is ful...

[Page 13] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 13 of 31 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between t...

[Page 14] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 14 of 31 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SH...

[Page 15] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 15 of 31 TAP Controller Block Diagram TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter Description Test Conditions Min Max U...

[Page 16] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 16 of 31 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK ...

[Page 17] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 17 of 31 Identification Register Definitions Instruction Field Value Description CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 Revision Number (31:2...

[Page 18] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 18 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 26N 299G 566A 831J 3 7...

[Page 19] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 19 of 31 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up S...

[Page 20] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 20 of 31 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ........

[Page 21] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 21 of 31 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 575 mA (x9) 580 (x18) 600 (x36) 635 167 MHz (x8) 49...

[Page 22] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 22 of 31 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Uni...

[Page 23] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 23 of 31 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consortium Parameter Description 300 MHz 278 MHz 250 MHz 200 MHz ...

[Page 24] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 24 of 31 Output Times t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX D...

[Page 25] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 25 of 31 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [26, 27, 28] READ READREAD NOP NOP WRITEWRITE NOP 1 2345678910 Q40 t KHCH t CO t t HC ...

[Page 26] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 26 of 31 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit...

[Page 27] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 27 of 31 250 CY7C1316BV18-250BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1916BV18-250BZC CY7C1318BV18-250BZC CY7C132...

[Page 28] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 28 of 31 167 CY7C1316BV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1916BV18-167BZC CY7C1318BV18-167BZC CY7C132...

[Page 29] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 29 of 31 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø0.25MCAB �...

[Page 30] Cypress Semiconductor CY7C1316BV18

CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Document Number: 38-05621 Rev. *D Page 30 of 31 Document History Page Document Title: CY7C1316BV18/CY7C1916BV18/CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Ar- chitecture Document...

[Page 31] Cypress Semiconductor CY7C1316BV18

Document Number: 38-05621 Rev. *D Revised June 2, 2008 Page 31 of 31 DDR RAMs and QDR RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC, and Samsung. All product and company names mentioned in this document are th...