Xilinx NOTFOUND V2.1 Reference Manual

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— Printed in U.S.A. Xilinx System Generator v2.1 for Simulink User Guide Xilinx Blockset Reference Guide Introduction Xilinx Blockset Overview Xilinx Blocks System Generator Software Features Using the Xilinx Software Auxiliary Files ...

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2 Xilinx Development System Xilinx System Generator v2.1 Reference Guide About This Manual This document is a reference guide for system designers who are unfamiliar with the System Generator v2.1 and the Xilinx Blockset. Manual Contents This guide c...

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3 Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some additional resources. Resource Description/URL IP Center Information on Xilinx LogiCOREs and IP solutions. http://www.xilinx.com/ipcent...

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4 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Conventions This document uses the following conventions. An example illustrates each convention. Typographical The following conventions are used for all System Generator docum...

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5 Contents Chapter 1 Introduction Industry and Product Overview .................................................................................8 System Generator .........................................................................................

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6 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Concat .................................................................................................................30 Constant ................................................

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7 Gateway Out.........................................................................................................99 Quantization Error Blocks ....................................................................................101 Display ..........

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8 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Chapter 1 Introduction This chapter describes the basic concepts and tools of the System Generator v2.1. This chapter contains the following sections. • Industry and Product O...

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System Generator 9 Introduction constructs for simulation, its synthesizable subset is far too restrictive for system design. System Generator is a software tool for modeling and designing FPGA-based DSP systems in Simulink. The tool presents a high ...

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10 Xilinx Development System Xilinx System Generator v2.1 Reference Guide 3 and simply use floating point operations in hardware. The answer is that most operations have a sufficiently smalldynamic range that a fixed point representationis accepta...

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The System Generator Design Flow 11 Introduction The System Generator design flow is shown in the following figure. Figure 1-1: System Generator design flow diagram The Xilinx Blockset is accessible in the Simulink library browser, and elements ...

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12 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Simulink hierarchy into a hierarchical VHDL netlist. In addition, System Generator creates the necessary command files to create the IP block netlists using CORE Generator...

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Hardware Handshaking 13 Introduction Generator then propagates signal types and precisions as appropriate. The automatically chosen type is the least expensive that preserves full precision. Translations from signed to unsigned and vice versa are au...

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14 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Bit-True and Cycle-True Modeling System Generator produces a hardware implementation that is bit and cycle true to the system level simulation. We define the term bit and cycl...

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What is a Xilinx Block? 15 Xilinx Blockset Overview Chapter 2 Xilinx Blockset Overview This chapter gives an overview of the Xilinx Blockset, including background information on underlying blockset implementation, which will help you understand how e...

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16 Xilinx Development System Xilinx System Generator v2.1 Reference Guide portion of a Simulink model to be implemented in an FPGA must be built exclusively of Xilinx blocks, with the exception of subsystems denoted as black boxes. Instantiating Xili...

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The Nature of Signals in the Xilinx Blockset 17 Xilinx Blockset Overview As an example, the figures shown below depict the Xilinx Negate block parameters dialog box with full and user defined precision. Note in the latter case the additional option...

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18 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Use of Xilinx Smart-IP Cores by the System Generator To increase hardware performance, most System Generator blocks are implemented using Xilinx Smart-IP (Intellectual Property...

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Common Options in Block Parameters Dialog Box 19 Xilinx Blockset Overview Xilinx LogiCORE  Versions The Xilinx LogiCORE blocks (indicating the version numbers being supported by the System Generator) used in Xilinx System Generator v2.1 are li...

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20 Xilinx Development System Xilinx System Generator v2.1 Reference Guide specific parameters are described in the specific block documentation in the next chapter. The remainder of the parameters in each block’s parameters dialog box are common ...

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Common Options in Block Parameters Dialog Box 21 Xilinx Blockset Overview Precision The fundamental computational mode in the Xilinx Blockset is arbitrary precision fixed point arithmetic. Most blocks give you the option of choosing the precision, ...

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22 Xilinx Development System Xilinx System Generator v2.1 Reference Guide In the Simulink environment, the Override with Doubles option allows you to simulate the entire design in double precision floating point. This option is useful in selecting �...

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Basic Elements 23 Xilinx Blocks Chapter 3 Xilinx Blocks This chapter describeseach Xilinxblock in detail.Xilinx blocksaregroupedwithin six categories, also shown in the Simulink library browser. They are: • Basic Elements • Communication • DSP ...

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24 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-1: System Generator block parameters d...

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Basic Elements 25 Xilinx Blocks The wrapper file is named to match the top level VHDL file generated for your project. For example, if your top level file is named design_project, the wrapper is called design_project_testbench.vhd. The top level o...

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26 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Addressable Shift Register The Xilinx Addressable Shift Register block is a variable-length shift register (or delay chain). This block differs from the Xilinx Delay block in ...

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Basic Elements 27 Xilinx Blocks Block Parameters Dialog Box The Addressable Shift Register Block Parameters Dialog Box can be invoked by double-clicking the icon in your Simulink model. Figure 3-2: Addressable Shift Register block parameters dialog...

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28 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Black Box The Xilinx Black Box token enables you to instantiate your own specialized functions in your model, and subsequently into a generated design. Like the System Generato...

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Basic Elements 29 Xilinx Blocks infer them in the generated VHDL. The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-3: Black Box block parameters dialog box Parameters specified as cell arr...

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30 Xilinx Development System Xilinx System Generator v2.1 Reference Guide input and output ports respectively. To configure the black box, enter the parameters in the black box block parameters dialog box as shown in the figure below. Figure 3-4: ...

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Basic Elements 31 Xilinx Blocks Constant The Xilinx Constant block generatesa constant. This block is similar to the Simulink constant block, but can be used to drive the inputs on Xilinx blocks. Block Parameters Dialog Box The block parameters dialo...

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32 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-7: Convert block parameters dialog box...

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Basic Elements 33 Xilinx Blocks The block can be configured as a free running up or down counter by selecting the Provide Reset Pin option on the block parameters dialog box. In this case,the blockhas a resetinput port in addition toits output port....

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34 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The Counter block parameters dialog box is invoked by double-clicking the block icon. Figure 3-8: Counter block parameters dialog box Parameters s...

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Basic Elements 35 Xilinx Blocks Xilinx LogiCORE The block always uses the Xilinx LogiCORE: Binary Counter V5.0. The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\binary_counter.pdf...

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36 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Down Sample The Xilinx Down Sample block reduces the sample rate at the point where the block is placed in your design. The input signal is under- sampled so that every nth inp...

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Basic Elements 37 Xilinx Blocks Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-12: Down sample block parameters dialog box Parameters specific to the block ar...

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38 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Mux The Xilinx Mux block implements a multiplexer. The block has one select input (type unsigned) and a user- configurable number ofdata bus inputs,ranging from 2 to 32. Block...

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Basic Elements 39 Xilinx Blocks %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\bus_mux.pdf Parallel to Serial The Parallel to Serial block takes an input word and splits it into N time multiplexed output words where N equals the num...

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40 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box Figure 3-15: Parallel to Serial block parameters dialog box Parameters specific to the block are: • Output Order: Most significant word first...

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Basic Elements 41 Xilinx Blocks Block Interface The block has one input port for the data and an optional input reset port. The initial output value is specified by the user in the block parameters dialog box (below). Data presented at the input wil...

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42 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Reinterpret The Reinterpret block forces its output to a new type without any regard for retaining the numerical value represented by the input. The binary representationispass...

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Basic Elements 43 Xilinx Blocks Block Parameters Dialog box Figure 3-17: Reinterpret block parameters dialog box Parameters specific to the block are: • Force Arithmetic Type: When checked, the Output Arithmetic Type parameter can be set and the...

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44 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The following waveform illustrates the block’s behavior: Figure 3-18: Example of Serial to Parallel behavior This example illustrates the case where the input width is 1, o...

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Basic Elements 45 Xilinx Blocks • Binary Point: Output binary point location Other parameters usedby this blockare explainedinthe Common Parameterssection of the previous chapter. The Parallel to Serial block does not use a Xilinx LogiCORE. An erro...

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46 Xilinx Development System Xilinx System Generator v2.1 Reference Guide only the first three fractional bits. The following diagram illustrates how to extract all but the top 16 and bottom 8 bits of the input. Figure 3-21: Slice block operation ...

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Basic Elements 47 Xilinx Blocks Figure 3-22: Slice block parameters dialog box showing different options Parameters specific to the block are: • Specify Range As: (Two Bit Locations | Upper Bit Location + Width |Lower Bit Location + Width). All...

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48 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The following diagram illustrates the operation of this block. Figure 3-23: Sync block use This diagram shows a two-channelXilinx SyncBlock connected to two signalsources, wi...

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Basic Elements 49 Xilinx Blocks It is instructive to note that the following model produces behavior identical to the one with the Sync block. This one, though, requires the designer to examine the two upstream pipelined sources and to insert the cor...

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50 Xilinx Development System Xilinx System Generator v2.1 Reference Guide added to the channel that is last to present a valid input sample. Note that if this parameter is zero, the block has a feed-through path; otherwise, it does not. Other paramet...

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Basic Elements 51 Xilinx Blocks from din to dout. Whenever possible, put a register or delay block after an up sample block. Figure 3-28: Example of up sample block behavior with zero padding Block Parameters Dialog Box The block parameters dialog ...

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52 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Communication The blocks in the Communication library implement functions used in digital communications systems, including convolutional and block channel coding, interleaving...

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Communication 53 Xilinx Blocks Block Parameters Dialog Box The following figure shows the block parameters dialog box. Figure 3-31: Convolutional encoder block parameters dialog box Parameters specific to the block are: • Output Rate: 2 or 3. N...

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54 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Depuncture The Xilinx Depuncture block allows you to insert arbitrary symbol into your input data at the location specified by the depuncture code and creates a new value. Th...

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Communication 55 Xilinx Blocks Block Parameters Dialog Box The Xilinx depuncture block can be configured using its Block Parameters dialog box. Figure 3-33: Depuncture block parameters dialog box Parameters specific to the Xilinx Puncture block a...

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56 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Figure 3-34: Forney convolutional interleaver with a constant difference between consecutive branches When the block is in deinterleaver mode, the input data sampled on the D...

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Communication 57 Xilinx Blocks When the branch lengths are specified as an array, the block operates the same in either interleaver or deinterleaver mode because the array fully defines the length of all the branches. The array must have length B,...

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58 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The Core datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\sid_v1_1\doc\sid .pdf This is a licensed core, available for purchase on th...

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Communication 59 Xilinx Blocks Block Parameters Dialog Box The Xilinx puncture block can be configured using its Block Parameters dialog box. Figure 3-38: Puncture block parameters dialog box Parameters specific to the Xilinx Puncture block are: ...

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60 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The probability of each of the three outcomes depends on the particular Reed- Solomon code and the nature of the communications channel. The Simulink blocksets provide excellen...

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Communication 61 Xilinx Blocks Block Parameters Dialog Box The RS Decoder block can be configured using its Block Parameters dialog box. Figure 3-40: Reed-Solomon Decoder block parameters dialog box Parameters specific to the RS Decoder block are...

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62 Xilinx Development System Xilinx System Generator v2.1 Reference Guide ♦ IESS-308 (208): implements IESS-308 specification (208, 192) shortened RS code. ♦ IESS-308 (219): implements IESS-308 specification (219, 201) shortened RS code. ♦ IE...

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Communication 63 Xilinx Blocks • Scaling Factor: Scaling factor for the generator polynomial root index. Normally h is 1; however, it can be any positive integer between 1 and (2 16 -1). • Provide Start Pin: when checked, the block has optional s...

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64 Xilinx Development System Xilinx System Generator v2.1 Reference Guide type of errors that can be corrected depends on the characteristics of the Reed- Solomon code. Reed-Solomon codes are a subset of BCH (Bose, Chaudhuri, and Hocquenghem) codes a...

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Communication 65 Xilinx Blocks Block Interface The Xilinx RS Encoder block has two inputs (din, rst) and three output (dout, info and rfd) ports. The RS Encoder block also has optional start and bypass input ports. Figure 3-43: Reed-Solomon Encoder...

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66 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The RS Encoder block can be configured using its Block Parameters dialog box. Figure 3-44: Reed-Solomon Encoder block parameters dialog box Param...

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Communication 67 Xilinx Blocks ♦ IESS-308 (225): implements IESS-308 specification (225, 205) shortened RS code. • Symbol Width: specifies the symbol width for the RS code. The RS encoder supports symbol width from 3 to 12. • n: specifies th...

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68 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Other parameters used by thisblock are described in the Common Parameterssection of the previous chapter. The RS Encoder block cannot be placed in an enabled subsystem in Syste...

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Communication 69 Xilinx Blocks Block Interface The Viterbi Decoder has either twoor three input ports and one output port. The decoder can have either two or three input ports depending on the configurable parameter indicating encoder output rate. U...

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70 Xilinx Development System Xilinx System Generator v2.1 Reference Guide • Traceback Length:Length ofthe tracebackthroughthe Viterbi trellis. Optimal length is considered to be between 5 and 7 times the constraint length. • Convolution Code 1: U...

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DSP 71 Xilinx Blocks Block Interface The CIC Block has one input and one output port. The input port can be between 1 and 32 bits (inclusive). The twobasic buildingblocks ofa CIC filter are theintegrator andthe comb. A single integrator is a single...

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72 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The CIC Block can be configured using its Block Parameters dialog box: Figure 3-47: CIC block parameters dialog box Parameters specific to this ...

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DSP 73 Xilinx Blocks DDS The Xilinx DDS Block implements a direct digital synthesizer (DDS), also commonly called a numerically controlled oscillator (NCO). The block employs a look-up table scheme to generate real or complex valued sinusoids. An i...

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74 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-49: DDS block parameters dialog box Pa...

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DSP 75 Xilinx Blocks • Phase Increment Type: specifies ∆θ to be either constant or register. Choice of register activates optional ports on the block. • Phase Increment: specifies value ofphase incrementconstant, a multipleof 2π. The numbe...

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76 Xilinx Development System Xilinx System Generator v2.1 Reference Guide for k=0, 1, ... , N-1, where is a principal N-th root of unity. The FFT block accepts as input a stream of complex data represented as a pair of Xilinx fixed point data and co...

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DSP 77 Xilinx Blocks • Memory Usage:number of memorybanks usedto computethe transform,one of Single, Double, Triple (not used for 16 point FFTs). • Scale Output By: one of 1/N or 1/(2N). • Overflow characteristic: block behavior when internal o...

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78 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Figure 3-52: FFT Timing Characteristics For 16-point FFTs, the block is always in the "ready for data" state and output frames aredeliveredcontinuously. Thus, there...

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DSP 79 Xilinx Blocks The Dual Port Block Memory LogiCORE datasheet can be found on your local disk at: %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemdp_v3_2\do c\dp_block_mem.pdf FIR The Xilinx FIR Filter Block implements a finite-impulse resp...

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80 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-53: FIR block parameters dialog box Pa...

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Math 81 Xilinx Blocks • Polyphase behavior: Decimation, Interpolation, Single rate. • Latency: specify input sample period latency. • Hardware Over-Sampling Rate: Hardware clocks per sample. This affects hardware implementation only, and has no...

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82 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-54: Accumulator block parameters dialo...

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Math 83 Xilinx Blocks %XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\accum.pdf AddSub The Xilinx AddSub block implements an adder/subtractor. The operation can be fixed (Add or Subtract) or changed dynamically under control of the ...

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84 Xilinx Development System Xilinx System Generator v2.1 Reference Guide uses the Xilinx LogiCORE Adder Subtractor V5.0. Otherwise, the block is implemented as a synthesizable VHDL module. The Core datasheet can be found on your local disk at: %XILI...

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Math 85 Xilinx Blocks saturated as needed. A positive value is implemented as an unsigned number, a negative value as signed. • Number of Bits in Constant: specifiesthe bit location of thebinary pointof the constant, where bit zero is the least si...

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86 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-57: Inverter block parameters dialog b...

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Math 87 Xilinx Blocks Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-58: Logical block parameters dialog box Parameters specific to the block are: • Logical...

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88 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Mult The Xilinx Mult block implements a multiplier. It computes the product of the data on its two input ports, producing the result on its output port. The block supports a si...

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Math 89 Xilinx Blocks Figure 3-60: Mult block parameters dialog box - sequential type Parameters specific to the Mult block are: • Multiplier Type: directs the implementation to be either parallel or sequential. • Require Maximum Pipelining: d...

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90 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Negate The Xilinx Negate block computes the arithmetic negation (two’s complement) of its input. The block can be implemented either as a Xilinx LogiCORE or as a synthesizabl...

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Math 91 Xilinx Blocks ♦ equal-to (a = b) ♦ not-equal-to (a != b) ♦ less-than (a < b) ♦ greater-than (a > b) ♦ less-than-or-equal-to (a <= b) ♦ greater-than-or-equal-to (a >= b) The output ofthe block isa 1-bit unsignednumber. ...

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92 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Scale The Xilinx Scale block scales its input by a power of two. The power can be either positive or negative. The block has one input and one output. The scale operation hasth...

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Math 93 Xilinx Blocks Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-64: Shift block parameters dialog box Parameters specific to the Shift block are: • Shi...

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94 Xilinx Development System Xilinx System Generator v2.1 Reference Guide fundamental sinusoid lie in the half-open interval [-1, 1]. If you need a balanced representation, one canbe builtusing the SinglePort RAMblock with theappropriate initializat...

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Math 95 Xilinx Blocks 64. This corresponds to one CLB per output bit. If the table depth is greater than 64, a quarterwave is stored, and additional logicis used to generatethe remainingportions of the wave. Storing only the quarter wave for the lar...

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96 Xilinx Development System Xilinx System Generator v2.1 Reference Guide Block Parameters Dialog Box The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-66: Threshold block parameters dialog ...

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MATLAB I/O 97 Xilinx Blocks LogiCOREs, as well as signals and control circuits to drive the clock network. Consequently, most System Generator blocks do not provide an explicit enable port. There are two exceptions> the Register block and the Addr...

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98 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-68: Gateway In block parameters dialog box Parameters specific to...

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MATLAB I/O 99 Xilinx Blocks It should be noted there is a valid bit that accompanies the data signal. It is constrained at the same rate. For more information concerning the valid bit, refer to the Hardware Handshaking section in Chapter 1 of this m...

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100 Xilinx Development System Xilinx System Generator v2.1 Reference Guide The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model. Figure 3-69: Gateway Out block parameters dialog box Parameters specific ...