Intel SL3VS - Celeron 633 MHz Processor Specification

[Page 1] Intel SL3VS - Celeron 633 MHz Processor

Intel ® Celeron ® Processor Specification Update Release Date: August 2007 Document Number: 243748-051 The Intel ® Celeron ® processor may contain design defects or errors known as errata, which may cause the produ...

[Page 2] Intel SL3VS - Celeron 633 MHz Processor

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS...

[Page 3] Intel SL3VS - Celeron 633 MHz Processor

i CONTENTS REVISION HISTORY....................................................................................................................................... ii PREFACE ..........................................................................

[Page 4] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON ® PROCESSOR SPECIFICATION UPDATE ii REVISION HISTORY Date of Revision Version Description April 1998 -001 This document is the first Specification Update for the Intel ® Celeron c processor. May 1998 -002 Adde...

[Page 5] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON ® PROCESSOR SPECIFICATION UPDATE iii REVISION HISTORY Date of Revision Version Description August 1999 -017 Added Documentation Change C2. Updated Preface paragraph. Updated Codes Used in Summary Table. Updated column...

[Page 6] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON ® PROCESSOR SPECIFICATION UPDATE iv REVISION HISTORY Date of Revision Version Description July 2001 -035 Updated the Intel ® Celeron ® Processor Identification Information table. Updated the Summary of Errata tab...

[Page 7] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON ® PROCESSOR SPECIFICATION UPDATE v REVISION HISTORY Date of Revision Version Description August 2007 -051 Updated Summary Table of Changes. Added Erratum C111. ...

[Page 8] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON ® PROCESSOR SPECIFICATION UPDATE vi PREFACE This document is an update to the specifications contained in the following documents: • Pentium ® II Processor Developer’s Manual (Order Number 243502) • P6 Family of...

[Page 9] Intel SL3VS - Celeron 633 MHz Processor

Specification Update for the Intel ® Celeron ® Processor GENERAL INFORMATION Intel ® Celeron ® Processor and Boxed Intel ® Celeron ® Processor Markings (S.E.P. Package) ® i m ©’98 celeron ™ Static White Silkscreen marks 266...

[Page 10] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 2 Intel ® Celeron ® Processor and Boxed Intel ® Celeron ® Processor Markings (PPGA Package) celeron TM AAAAAAAZZZ LLL SYYYY Country of Origin FFFFFFFF-XXXX M C ’98 i Top Bo...

[Page 11] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 3 Intel ® Celeron ® Processor and Boxed Intel ® Celeron ® Processor Markings (FC-PGA/FC-PGA2 Package) FC-PGA 370 Pin Package GRP1LN1: INTEL (m)(c) '01_-_{COO} GRP1LN2: {Core F...

[Page 12] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 4 IDENTIFICATION INFORMATION Complete identification information of the Celeron processor can be found in the Intel Processor Identification and the CPUID Instruction application note (Docum...

[Page 13] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 5 Intel ® Celeron ® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) CPUID Speed (MHz) Core/Bus Package and Revision Notes SL2SY A0 0 0650h ...

[Page 14] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 6 Intel ® Celeron ® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) CPUID Speed (MHz) Core/Bus Package and Revision Notes SL3A2 B0 128 0665h ...

[Page 15] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 7 Intel ® Celeron ® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) CPUID Speed (MHz) Core/Bus Package and Revision Notes SL48F B0 128 0683...

[Page 16] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 8 Intel ® Celeron ® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) CPUID Speed (MHz) Core/Bus Package and Revision Notes SL634 D0 128 068Ah ...

[Page 17] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 9 Intel ® Celeron ® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) CPUID Speed (MHz) Core/Bus Package and Revision Notes SL5XT D0 128 068Ah ...

[Page 18] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 10 Intel ® Celeron ® Processor Identification Information S-Spec Core Stepping L2 Cache Size (Kbytes) CPUID Speed (MHz) Core/Bus Package and Revision Notes SL6C6 B1 256 06B4h...

[Page 19] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 11 SUMMARY OF CHANGES The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Celeron processors. Intel intends t...

[Page 20] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 12 AC = Intel ® Celeron® Processor in 478 Pin Package AD = Intel ® Celeron® D processor on 65 nm process AE = Intel ® Core™ Duo Processor and Intel ® Core™ Solo processor on 6...

[Page 21] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 13 Summary of Errata NO. CPUID/Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 cache line replacement C11 X X X X ...

[Page 22] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 14 Summary of Errata NO. CPUID/Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 C26 X X X X Fixed Test pin must be ...

[Page 23] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 15 Summary of Errata NO. CPUID/Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 C40 X X X X Fixed Incorrect chunk o...

[Page 24] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 16 Summary of Errata NO. CPUID/Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 C53 X X X X X NoFix FLUSH# servicing delayed ...

[Page 25] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 17 Summary of Errata NO. CPUID/Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 C68 X NoFix Snoop probe during FLUSH# ...

[Page 26] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 18 Summary of Errata NO. CPUID/Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 SLP# is Asserted Low C82 X X NoFix Inc...

[Page 27] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 19 Summary of Errata NO. CPUID/Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 (Uncacheable) May Consolidate to UC C93 X X X ...

[Page 28] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 20 Summary of Errata NO. CPUID/Stepping Plans ERRATA 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 Have Not Occurred C101 X X X X X X X X X NoF...

[Page 29] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 21 * Fix will be only on Celeron processors with CPUID=068xh. Summary of Documentation Changes CPUID/Stepping NO. 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1...

[Page 30] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 22 Summary of Documentation Changes CPUID/Stepping NO. 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 Plans DOCUMENTATION CHANGES C22 X X X X X X X X ...

[Page 31] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 23 Summary of Specification Clarifications CPUID/Stepping NO. 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 Plans SPECIFICATION CLARIFICATIONS C1 X...

[Page 32] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 24 Summary of Specification Changes CPUID/Stepping NO. 650h A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1 Plans SPECIFICATION CHANGES C1 X X X X X X X ...

[Page 33] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 25 ERRATA C1. FP Data Operand Pointer May Be Incorrectly Calculated After FP Access Which Wraps 64-Kbyte Boundary in 16-Bit Code Problem: The FP Data Operand Pointer is the effective addres...

[Page 34] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 26 b) causes the page table Access or Dirty (A/D) bits to be modified, the breakpoint information for the MOVSS or POPSS will be lost. Previous Celeron processors retain this information und...

[Page 35] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 27 C4. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for ...

[Page 36] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 28 C6. I/O Restart in SMM May Fail After Simultaneous MCE Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction be...

[Page 37] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 29 C9. LBER May Be Corrupted After Some Events Problem: The last branch record (LBR) and the last branch before exception record (LBER) can be used to determine the source and destination in...

[Page 38] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 30 C11. Potential Early Deassertion of LOCK# During Split-Lock Cycles Problem: During a split-lock cycle there are four bus transactions: 1st ADS# (a partial read), 2nd ADS# (a partial read...

[Page 39] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 31 Status: For the steppings affected see the Summary of Changes at the beginning of this section. C13. Reporting of Floating-Point Exception May Be Delayed Problem: The Celeron processor no...

[Page 40] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 32 C15. Built-in Self Test Always Gives Nonzero Result Problem: The Built-in Self Test (BIST) of the Celeron processor does not give a zero result to indicate a passing test. Regardless of p...

[Page 41] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 33 C18. Snoop Cycle Generates Spurious Machine Check Exception Problem: The processor may incorrectly generate a Machine Check Exception (MCE) when it processes a snoop access that does not ...

[Page 42] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 34 3. The unmasked floating-point exception case only occurs if the store is the first MMX technology instruction in an MMX technology routine and the previous floating-point routine exited w...

[Page 43] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 35 Workaround: If the chipset and third party agents used with the Celeron processor do not optimize their arbitration latency as described above, no action is required. For the 66 MHz Celeron...

[Page 44] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 36 C23. MOVD Following Zeroing Instruction Can Cause Incorrect Result Problem: An incorrect result may be calculated after the following circumstances occur: 1. A register has been zeroed ...

[Page 45] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 37 Workaround: There are two possible workarounds for this erratum: 1. Rather than using the MOVSX-MOVD or CBW-MOVD pairing to handle one variable at a time, use the sign extension capabili...

[Page 46] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 38 C25. Read Portion of RMW Instruction May Execute Twice Problem: When the Celeron processor executes a read-modify-write (RMW) arithmetic instruction, with memory as the destination, it is...

[Page 47] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 39 Status: For the steppings affected see the Summary of Changes at the beginning of this section. C28. MC2_STATUS MSR Has Model-Specific Error Code and Machine Check Architecture Error Code...

[Page 48] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 40 C30. Upper Four PAT Entries Not Usable With Mode B or Mode C Paging Problem: The Page Attribute Table (PAT) contains eight entries, which must all be initialized and considered when sett...

[Page 49] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 41 C32. Misprediction in Program Flow May Cause Unexpected Instruction Execution Problem: To optimize performance through dynamic execution technology, the P6 architecture has the ability t...

[Page 50] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 42 Workaround: All bus agents that support system bus ECC must disable it when a 2:1 ratio is used. Status: For the steppings affected see the Summary of Changes at the beginning of this secti...

[Page 51] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 43 C37. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and CS Registers Problem: According to the processor specification, attempting to load a null segm...

[Page 52] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 44 C39. Far Jump to New TSS With D-bit Cleared May Cause System Hang Problem: A task switch may be performed by executing a far jump through a task gate or to a new Task State Segment (TSS)...

[Page 53] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 45 C41. UC Write May Be Reordered Around a Cacheable Write Problem: After a write occurs to a UC (uncacheable) region of memory, there exists a small window of opportunity where a subsequent...

[Page 54] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 46 C43. Internal Cache Protocol Violation May Cause System Hang Problem: A Celeron processor-based system may hang due to an internal cache protocol violation. During multiple transactions t...

[Page 55] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 47 C45. Machine Check Exception May Occur Due to Improper Line Eviction in the IFU Problem: The Celeron processor is designed to signal an unrecoverable Machine Check Exception (MCE) as a c...

[Page 56] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 48 C47. Task Switch May Cause Wrong PTE and PDE Access Bit to be Set Problem: If an operating system executes a task switch via a Task State Segment (TSS), and the TSS is wholly or partiall...

[Page 57] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 49 C49. Deadlock May Occur Due To Illegal-Instruction/Page-Miss Combination Problem: Intel's 32-bit Instruction Set Architecture (ISA) utilizes most of the available op-code space; how...

[Page 58] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 50 C51. Floating-Point Exception Condition May be Deferred Problem: A floating-point instruction that causes a pending floating-point exception (ES=1) is normally signaled by the processor o...

[Page 59] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 51 C53. FLUSH# Servicing Delayed While Waiting for STARTUP_IPI in 2-way MP Systems Problem: In a 2-way MP system, if an application processor is waiting for a startup inter-processor interru...

[Page 60] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 52 C55. MCE Due to L2 Parity Error Gives L1 MCACOD.LL Problem: If a Cache Reply Parity (CRP) error, Cache Address Parity (CAP) error, or Cache Synchronous Error (CSER) occurs on an access to...

[Page 61] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 53 C57. Mixed Cacheability of Lock Variables Is Problematic in MP Systems Problem: This errata only affects multiprocessor systems where a lock variable address is marked cacheable in one p...

[Page 62] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 54 C59. Potential Loss of Data Coherency During MP Data Ownership Transfer Problem: In MP systems, processors may be sharing data in different cache lines, referenced as line A and line B i...

[Page 63] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 55 C61. Memory Ordering Based Synchronization May Cause a Livelock Condition in MP Systems Problem: In an MP environment, the following sequence of code (or similar code) in two processors (...

[Page 64] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 56 C62. Processor May Assert DRDY# on a Write With No Data Problem: When a MASKMOVQ instruction is misaligned across a chunk boundary in a way that one chunk has a mask of all 0’s, the pro...

[Page 65] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 57 Status: For the steppings affected, see the Summary of Changes at the beginning of this section. C66. MASKMOVQ Instruction Interaction with String Operation May Cause Deadlock Problem: U...

[Page 66] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 58 or IMUL AX, word ptr <memory address> (opcode 0F AF /r) or IMUL AX, BX, 16 (opcode 6B /r ib) or IMUL AX, word ptr <memory address>, 16 (opcode 6B /r ib) or IMUL AX, 8 (opco...

[Page 67] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 59 *Note: MOV EAX, EAX is used here in a generic sense. Again, EAX can be substituted with any 32-bit register. Status: For the steppings affected see the Summary of Changes at the beginn...

[Page 68] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 60 C70. Selector for the LTR/LLDT Register May Get Corrupted Problem: The internal selector portion of the respective register (TR, LDTR) may get corrupted if, during a small window of LTR o...

[Page 69] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 61 C73. Memory Aliasing with Inconsistent A and D bits May Cause Processor Deadlock Problem: In the event that software implements memory aliasing by having two Page Directory Entries(PDEs)...

[Page 70] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 62 C76. Machine Check Exception may Occur When Interleaving Code Between Different Memory Types Problem: A small window of opportunity exists where code fetches interleaved between different...

[Page 71] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 63 C79. The instruction Fetch Unit (IFU) May Fetch Instructions Based Upon Stale CR3 Data After a Write to CR3 Register Problem: Under a complex set of conditions, there exists a one c...

[Page 72] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 64 C82. Incorrect Assertion of THERMTRIP# Signal Problem: The internal control register bit responsible for operation of the Thermtrip circuit functionality may power up in a non-in...

[Page 73] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 65 Figure 1 Celeron® on 0.13 Micron Processor 256K Platforms Workaround Status: For the steppings affected, see the Summary of Changes at the beginning of this section. ...

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INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 66 C83. Under Some Complex Conditions, the Instructions in the shadow of a JMP FAR may be Unintentionally Executed and Retired Problem: If all of the following events happen in sequence...

[Page 75] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 67 C85. Lock Data Access that Spans Two Pages May Cause the System to Hang Problem: An instruction with lock data access that spans across two pages may, given some rare internal cond...

[Page 76] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 68 C87. The FXSAVE, STOS, or MOVS Instructions May Cause a Store Ordering Violation When Data Crosses a Page with a UC Memory Type Problem: If the data from an FXSAVE, STOS, or MOVS in...

[Page 77] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 69 Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system. Workaround: Avoid code t...

[Page 78] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 70 Status: For the steppings affected, see the Summary Tables of Changes. C92. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Combine) While Associated M...

[Page 79] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 71 Problem: A load from memory type USWC may get its data internally forwarded from a pending store. As a result, the expected load may never be issued to the external bus. Implication: W...

[Page 80] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 72 Implication: This erratum may cause an unexpected stack overflow. Workaround: User mode code should not count on being able to recover from illegal accesses to memory regions protected wi...

[Page 81] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 73 Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that acce...

[Page 82] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 74 • a linear address has bit 20 set • the address references a large page • A20M# is enabled Implication: When A20M# is enabled and an address references a large page the resul...

[Page 83] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 75 Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE) registers before writing to memory early in BIOS code to clear all the global entries from TLB. ...

[Page 84] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 76 • INT1 instruction; • Code breakpoint the DR6 BS (Single Step, bit 14) flag may be incorrectly set. Implication: The BS flag may be incorrectly set for non-single-step #DB except...

[Page 85] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 77 C108: INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffe...

[Page 86] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 78 C111 Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions fro...

[Page 87] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 79 DOCUMENTATION CHANGES The Documentation Changes listed in this section apply to the following documents: • Pentium ® II Processor Developer’s Manual • P6 Family of Processors Ha...

[Page 88] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 80 C2. Executing the SSE2 Variant on a Non-SSE2 Capable Processor In Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference the section for each of the ...

[Page 89] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 81 It should state: "If FOP code compatibility mode is enabled, the FOP is defined as it has always been in previous IA32 implementations (always defined as the FOP of the last non-tr...

[Page 90] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 82 The Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture Section 3.7.2, Figure 3.7. “EFLAGS Register” currently states: Bit 11 “OF” as “X” It...

[Page 91] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 83 The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference Appendix A, Table A-2, the opcode corresponding to 0x33 currently states: Gb, Ev It should sta...

[Page 92] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 84 The following changes will be made to the Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference: 1. Page 3-586 “PMULUDQ—Multiply Packed Unsigned...

[Page 93] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 85 PMOVMSKB (66) Gd, Vdq 5 . Page A-10, Table A-3, Two-byte Opcode Map:80H-7FH (First Byte is 0FH). Entry F7 currently states: MASKMOVQ Ppi, Qpi MASKMOVQU (66) Vdq, Wdq...

[Page 94] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 86 PMULH – Packed multiplication It should state: PMULHW – Packed multiplication, store high word 10. Page B-21, Table B-12, MMX Instruction Formats and Encodings (Contd.). ...

[Page 95] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 87 15. Page B-41, Table B-19, Formats and Encodings of the SSE2 SIMD Integer Instruction. Entry PMULL currently states: PMULL – Packed multiplication It should state: PMULLW...

[Page 96] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 88 The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference page 3-173 currently states: Operation IF (((AL AND 0FH) > 9) or AF = 1) THEN ...

[Page 97] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 89 The Intel Architecture Software Developer's Manual, Vol 2: Instruction Set Reference, on page 3-175 currently states: Operation IF (AL AND 0FH) > 9 OR AF = 1 THEN ...

[Page 98] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 90 The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Chapter 15, Section 5.3, on page 15-15 currently states: 15.5.3. Monitoring Branches, Exceptio...

[Page 99] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 91 The Intel Architecture Software Developer's Manual, Vol 1: Basic Architecture, page 12-6, section 12.5.2, last paragraph currently states: If the I/O bit map base address is gre...

[Page 100] Intel SL3VS - Celeron 633 MHz Processor

INTEL ® CELERON® PROCESSOR SPECIFICATION UPDATE 92 The Intel Architecture Software Developer's Manual, Vol 3: System Programming Guide Section 15.9.6 " Programming the Performance Counters for Non-Retirement Events" ...