NEC PD75402A User's Manual

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[Page 1] NEC PD75402A

USER'S MANUAL µ PD75402A 4-BIT SINGLE-CHIP MICROCOMPUTER µ PD75402A µ PD75P402 Document No. IEU1270C (O. D. No. IEU-644D) Date Published March 1994 P Printed in Japan© NEC Corporation 1989 ...

[Page 2] NEC PD75402A

The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for...

[Page 3] NEC PD75402A

Major Revisions in This Version Section Description Amendment: Fig. 5-52 “Data Transmission from Slave Device to Master Device” Change: Appendix B “Development Tools” P.117 P.179 to 181 The mark ★ shows main revised points. ...

[Page 4] NEC PD75402A

PREFACE USER This manual is intended for user engineers who wish to understand the µ PD75402A’s, 75P402’s functions and design an application system using them. OBJECTIVE The objective of this manual is for the user to understand the µ PD7540...

[Page 5] NEC PD75402A

Related Documentation Device Related Documents Document Name Document Number IE-75000-R/IE-75001-R User's Manual EEU-846 IE-75000-R-EM User's Manual EEU-673 EP-75402C-R User's Manual EEU-701 EP-75402GB-R User's Manual EEU-702 PG-1...

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- i - CONTENTS CHAPTER 1. GENERAL............................................................................................................................... 1 1.1 OUTLINE OF FUNCTIONS . .............................................................

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- ii - CHAPTER 4. INTERNAL CPU FUNCTIONS ........................................................................................... 31 4.1 PROGRAM COUNTER (PC) ........................................................................................

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- iii - 6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICING .............................................................................. 135 6.6 INTERRUPT APPLICATIONS .........................................................................................

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- iv - CONTENTS OF FIGURES Fig. No Title Page 3-1 Static RAM Address Updating Method ............................................................................................. 25 4-1 Program Counter Configuration ....................................

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- v - Fig. No. Title Page 5-32 Example of SBI Serial Bus System Configuration ........................................................................... 93 5-33 SBI Transfer Timing ......................................................................

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- vi - CONTENTS OF TABLES Table No. Title Page 1-1 Differences Between µ PD75402A and µ PD75402, 75P402 ................................................................. 4 2-1 Port Pin List .........................................................

[Page 12] NEC PD75402A

1 CHAPTER 1. GENERAL Name Program Memory Data Memory µ PD75402A 1920 × 8 (mask ROM) 64 × 4 (RAM) µ PD75P402 1920 × 8 (one-time PROM) 64 × 4 (RAM) CHAPTER 1. GENERAL The µ PD75402A, 75P402 is a CMOS 4-bit single-chip microcomputer adopting...

[Page 13] NEC PD75402A

2 CHAPTER 1. GENERAL Item Description 1.1 OUTLINE OF FUNCTIONS Number of basic instructions Instruction execution time Built-in memory General register Accumulators I/O line Pull-up resistor Clock output Timer/Counter Serial interface Vectored inte...

[Page 14] NEC PD75402A

3 CHAPTER 1. GENERAL Ordering Code Package Program Memory µ PD75402AC-××× 28-pin plastic DIP (600 mil) Mask ROM µ PD75402ACT-××× 28-pin plastic shrink DIP (400 mil) µ PD75402AGB-×××-3B4 44-pin plastic QFP ( ■ ■ 10mm) µ PD75P402C 28...

[Page 15] NEC PD75402A

4 CHAPTER 1. GENERAL Instruction execution time Port 5’s pull-up resistor Supply voltage Operating temperature range Package 1.3 DIFFERENCES BETWEEN µ PD75402A AND µ PD75402, 75P402 Table 1-1 shows the differences between the µ PD75402A and...

[Page 16] NEC PD75402A

5 CHAPTER 1. GENERAL  BASIC INTERVAL TIMER SERIAL INTERFACE INTERRUPT CONTROL INTBT INTCSI SI SO/SB0 SCK INT0 INT2 PROGRAM COUNTER(11) ROM (PROM)  PROGRAM MEMORY 1920 × 8 bits ALU�...

[Page 17] NEC PD75402A

6 CHAPTER 1. GENERAL 1.5 PIN CONFIGURATION 1.5.1 28-Pin Plastic Dip (600 mil), Shrink Dip (400 mil) (1) Normal operating mode P00 to P03 : Port 0 SCK : Serial clock input/output P10, P12 : Port 1 SO/SB0 : Serial output/input/output P20 to P23 : Po...

[Page 18] NEC PD75402A

7 CHAPTER 1. GENERAL (2) PROM mode A0 to A14 : Address input O0 to O7 : Data input/output CE : Chip enable input OE : Output enable input V DD : Power supply V PP : Program power supply V SS : Ground V PP A12 A7 A6 A5 A4 A3 A2�...

[Page 19] NEC PD75402A

8 CHAPTER 1. GENERAL P30 P31 P32 V SS P33 P60 P61 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 ...

[Page 20] NEC PD75402A

9 CHAPTER 1. GENERAL (2) PROM mode O0 O1 O2 NC NC V SS NC O3 O4 O5 NC A6 A7 A12 V PP NC NC NC V DD A14 A13 NC 1 2 3 4 5 6 7 8 9 10 11 23 24 25�...

[Page 21] NEC PD75402A

CHAPTER 2. PIN FUNCTIONS 10 CHAPTER 2. PIN FUNCTIONS The µ PD75402A operates by the pin functions in the normal operating mode. For the µ PD75P402’s pin functions, the 2 modes of the normal operating mode ( µ PD75402A mode) and the PROM ...

[Page 22] NEC PD75402A

11 CHAPTER 2. PIN FUNCTIONS Functions A 4-bit input port (Port 0). For P01 to P03, it is designatable to build in the pull-up resistor by software in 3-bit units. A 2-bit input port (Port 1). P10 is built in with the noise eliminator by the sampli...

[Page 23] NEC PD75402A

CHAPTER 2. PIN FUNCTIONS 12 Dual-Function Pin P10 P12 P03 P02/SB0 P01 P02/SO P22 2.1.2 List of Pins Other Than Port Pins Table 2-2 List of Pins Other than Port Pins Pin Name INT0 INT2 SI SO SCK SB0 PCL X1, X2 RESET VDD VSS NC*8 Functions An edge-...

[Page 24] NEC PD75402A

13 CHAPTER 2. PIN FUNCTIONS Port 0 Dual-Function Pin Port 1 Dual-Function Pin P00 P10 INT0 P01 SCK P12 INT2 P02 SO/SB0 P03 SI 2.2 NORMAL OPERATING MODE 2.2.1 P00 to P03 (Port 0) ..... SCK, SO/SB0, SI Dual-Function Input P10, P12 (Port 1) ..... INT...

[Page 25] NEC PD75402A

CHAPTER 2. PIN FUNCTIONS 14 2.2.2 P20 to P23 (Port 2) ..... PCL Dual-Function 3-Stae Input/Otput P30 to P33 (Port 3) ..... 3-State Input/Output P50 to P53 (Port 5) ..... N-ch Open Drain Middle-Voltage (10 V) Input/Output P60 to P63 (Port 6) ..... ...

[Page 26] NEC PD75402A

15 CHAPTER 2. PIN FUNCTIONS V DD V DD X1 X2 PD75402A µ Crystal Resonator or Ceramic Oscillator X1 X2 PD74HC04 µ External Clock (Standard 4.194304 MHz) PD75402A µ 2.2.7 X1, X2 (Crystal) The bu...

[Page 27] NEC PD75402A

CHAPTER 2. PIN FUNCTIONS 16 2.3 PROM MODE The PROM mode is designatable in the µ PD75P402 alone. 2.3.1 A0 to A14 (Address) ..... Input A 15-bit address input pin at PROM write/verify, read. As the PROM built into the µ PD75P402 has 2K bytes, i...

[Page 28] NEC PD75402A

17 CHAPTER 2. PIN FUNCTIONS Input/Output Type µ PD75402A µ PD75P402 P00 B P01/SCK F - A P02/SO/SB0 F - B P03/SI B - C P10/INT0 B P12/INT2 B - C P20, P21, P23 P22/PCL P30 to P33 E - B P50 to P53 M M - A P60 to P63 E - B RESET B 2.4 PIN INPUT/OUTP...

[Page 29] NEC PD75402A

CHAPTER 2. PIN FUNCTIONS 18 V DD P-ch P.U.R. enable IN P.U.R. V DD P-ch N-ch OUT data output disable V DD P-ch N-ch IN Type A (for Types E - B) Type B Type B - C Type D (for Type E - B, F - A, Y -...

[Page 30] NEC PD75402A

19 CHAPTER 2. PIN FUNCTIONS V DD IN/OUT N-ch (+10 V Withstand Voltage) data output disable P.U.R (Mask Option) IN/OUT N-ch (+10 V Withstand Voltage) data output disable Type F - B Type M Type M -...

[Page 31] NEC PD75402A

CHAPTER 2. PIN FUNCTIONS 20 V DD V DD V DD V DD Diode with Small V F P00, RESET P00, RESET 2.5 UNUSED PIN TREATMENT Pin P00 P01 to P03 P10 and P12 P20 to P23 P30 to P33 P50 to P53 P60 to P63 NC * If using the µ PD75P402 a...

[Page 32] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 21 CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP The µ PD75402A’s architecture is a subset of the 75X architecture. Its features are outlined below. 3.1 DATA MEMORY BANK CONFIG...

[Page 33] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 22 Adress 000H 003H 020H 03FH F80H FB0H FBFH FF0H FFFH Table 3-1 Data Memory Configuration and Address Range in Each Addressing Mode Addressing Mode Data Memory G...

[Page 34] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 23 Table 3-2 Addressing Mode List Addressing Mode 1-bit direct addressing 4-bit direct addressing 8-bit direct addressing 4-bit register indirect addressing Bit manipulation addressing Stack a...

[Page 35] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 24 3.1.2 Data Memory Addressing Modes In the µ PD75402A, the 6 types of addressing modes listed on Table 3-2 are available for the data memory space for efficient addressing per the bit leng...

[Page 36] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 25 (3) 8-bit direct addressing (mem) An addressing mode to specify the whole data memory space directly by the instruction’s operand per 8 bits. The specified memory bank (MB) is MB = 0 if t...

[Page 37] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 26 P30 P61 P53 (i) SET1 CY ; CY ← 1 AND1 CY, PORT3. 0 ; CY ∧P30 AND1 CY, PORT6. 1 ; CY ∧P61 SKT CY ; CY = 1? BR SETP CLR1 PORT5. 3 ;P53 ← 0 . . SETP: SET1 PORT5. 3 ; P53...

[Page 38] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 27 (6) Stack addressing This addressing mode is for the saving/restoring operation during the interrupting process, subroutine process. The data memory is addressed indirectly according to the...

[Page 39] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 28 3.2 MEMORY-MAPPED I/O The µ PD75402A adopts memory-mapped I/O to map such peripheral hardware as the input/output port, serial interface at addresses F80H to FFFH in the data memory space...

[Page 40] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 29 W W Bit 2 is fixed to 0. W W R/W R/W R/W R/W R/W R/W R/W R/W FB2H FB3H FB4H FB8H FBDH FBEH FBFH Bit 0 is fixed to 0. F80H F85H F86H W b3 b2 b1 b0 Stack pointer (SP) Basic interval timer mo...

[Page 41] NEC PD75402A

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP 30 * 1 * 2 * 3 W W W RR RR R/W R/W R/W R/W R/W R/W R/W R/W Port 0 (PORT 0) Port 1 (PORT 1) Port 2 (PORT 2) Port 3 (PORT 3) Port 5 (PORT 5) Port 6 (PORT 6) FF0H FF1H FF2H FF3H FF5H FF6H R/W Ser...

[Page 42] NEC PD75402A

CHAPTER 4. INTERNAL CPU FUNCTIONS 31 The program counter operates as follows. • Normal operation The content is incremented automatically according to the number of bytes of the instruction every time one is executed. • Branch instruction (BR...

[Page 43] NEC PD75402A

32 CHAPTER 4. INTERNAL CPU FUNCTIONS 4.2 PROGRAM MEMORY (ROM) ..... 1,920 WORDS × 8 BITS A mask programmable ROM of a 1,920-word × 8-bit configuration. It stores the program, table data, etc. The program memory is addressed by the program count...

[Page 44] NEC PD75402A

CHAPTER 4. INTERNAL CPU FUNCTIONS 33 4.3 DATA MEMORY (RAM) The data memory consists of the data and peripheral hardware areas as shown in Fig. 4-3. Fig. 4-3 Data Memory Map (1) Data area The µ PD75402A’s data area consists of the static RAM (...

[Page 45] NEC PD75402A

34 CHAPTER 4. INTERNAL CPU FUNCTIONS (2) Peripheral hardware area The peripheral hardware area is mapped to memory bank 15’s addresses F80H to FFFH. The operation is performed by the memory manipulation instruction just as in the static RAM. In...

[Page 46] NEC PD75402A

CHAPTER 4. INTERNAL CPU FUNCTIONS 35 4.4 GENERAL REGISTER ..... 4 × 4 BITS The general register is assigned to a specific address of the data memory. There are four 4-bit registers (H, L, X, A). While each general register is operated per 4 bits...

[Page 47] NEC PD75402A

36 CHAPTER 4. INTERNAL CPU FUNCTIONS 4.5 ACCUMULATOR In the µ PD75402A, the A register and the XA register pair function as accumulators. The 4-bit data process instruction is executed mainly by the A register and the 8-bit data process instruc...

[Page 48] NEC PD75402A

CHAPTER 4. INTERNAL CPU FUNCTIONS 37 4.6 STACK POINTER (SP) ..... 8 BITS The µ PD75402A uses a static RAM as the stack memory (LIFO format). The 8-bit register holding the top address information of such a stack memory area is the stack pointer...

[Page 49] NEC PD75402A

38 CHAPTER 4. INTERNAL CPU FUNCTIONS Fig. 4-8 Data Saved to Stack Memory Stack Stack Stack Register Pair Low Order Register Pair High Order SP - 2 SP - 1 SP SP - 2 SP - 1 SP SP - 4 SP - 3 PC10 - PC8...

[Page 50] NEC PD75402A

CHAPTER 4. INTERNAL CPU FUNCTIONS 39 4.7 PROGRAM STATUS WORD (PSW) ..... 8 BITS The program status word (PSW) consists of various flags concerning closely the processor operation. Fig. 4-10 shows its configuration. Saved to the stack memory per 8...

[Page 51] NEC PD75402A

40 CHAPTER 4. INTERNAL CPU FUNCTIONS Example Take AND of bit 3 at address 3FH and P33 and set the result in CY. SET1 CY ; CY← 1 SKT 3FH. 3 ; Skip if bit 3 at address 3FH is 1 CLR1 CY ; CY← 0 AND1 CY, PORT 3. 3 ; CY← CY ∧P33 (2) Skip flag ...

[Page 52] NEC PD75402A

41 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 DIGITAL INPUT/OUTPUT PORTS The µ PD75402A has the following digital input/output ports on chip: Ports 0 through 3, 5 and 6. The µ PD75402A uses memor...

[Page 53] NEC PD75402A

42 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.1 Digital Input/Output Port Types, Characteristics and Configuration The different types of digital input/output ports are shown in Table 5-1, and the configuration of each port is shown in Figs. 5-...

[Page 54] NEC PD75402A

43 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-2 Configuration of Ports 0 and 1 Input Buffer Internal Bus Input Buffer or f XX /64 Noise Elimination Circuit Input Buffer with Hysteresis Characteristics INT0INT2 P1...

[Page 55] NEC PD75402A

44 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-3 Configuration of Port 3 Remarks n = 0 to 3 Input Buffer PM 3 n=0 PM 3 n=1 M P X Output Latch PM 3 n PMGA Bit n Output Buffer POGA Bit 3 PO3 P-ch Pu...

[Page 56] NEC PD75402A

45 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-4 Configuration of Ports 2 and 6 * Input/output mode specification is performed by bit 2 (PM2) of PMGB for port 2 and by bits 4 to 7 (PM60 to 63) of PMGA for port 6. Remarks m = 2 or 6 Internal ...

[Page 57] NEC PD75402A

46 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-5 Configuration of Port 5 Pull-Up Resistors (Mask Option; µ PD75402A Only) 5.1.2 Input/Output Mode Setting The input/output mode for each input/output port is set by a port mode register as sh...

[Page 58] NEC PD75402A

47 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-6 Format of Port Mode Registers Port Mode Register Group A Port Mode Register Group B Specification 0 Input mode (output buffer off) 1 Output mode (output buffer on) Address 76543210 Symbol FE8H...

[Page 59] NEC PD75402A

48 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) Bit handling instructions Direct addressing of specific address bits (fmem.bit) can be used on all digital input/output ports. Example To OR P50 and P31 and output the result to P61. SET1 CY ; CY �...

[Page 60] NEC PD75402A

49 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.4 Digital Input/Output Port Operations Port and port pin operations when a data memory handling instruction is executed for a digital input/output port differ according to the input/output mode sett...

[Page 61] NEC PD75402A

50 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Table 5-3 Operations with Input/Output Port Handling Instructions SKT PORTn.bit SKF PORTn.bit AND1 CY, PORTn.bit OR1 CY, PORTn.bit XOR1 CY, PORTn.bit IN A, PORTn MOV A, PORTn OUT PORTn, A MOV PORTn, A ...

[Page 62] NEC PD75402A

51 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.5 Internal Pull-up Resistors The µ PD75402A can incorporate internal pull-up resistors for all port pins except P00 and P10. The µ PD75P402 can incorporate internal pull-up resistors for all po...

[Page 63] NEC PD75402A

52 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-7 Format of Pull-Up Resistor Specification Register Address 7 6 5 43210 Symbol FDCH – PO6 – – PO3 PO2 PO1 PO0 POGA Port 0 (P01 to P03) Port 1 (P12) Port 2 (P20 to P23) Port 3 (P30 to P33) ...

[Page 64] NEC PD75402A

53 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.1.6 Digital Input/Output Port Input/Output Timing The timing for outputting data to the output latch and fetching pin data or output latch data onto the internal bus is shown in Fig. 5-9. Fig. 5-9 Di...

[Page 65] NEC PD75402A

54 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.2 CLOCK GENERATION CIRCUIT The clock generation circuit supplies various clocks to the CPU and peripheral hardware, and controls the operating mode of the CPU. 5.2.1 Clock Generation Circuit Configura...

[Page 66] NEC PD75402A

55 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.2.2 Clock Generation Circuit Function and Operaion The clock generation circuit generates the CPU clock ( Φ ) and various clocks for supply to peripheral hardware, and controls the CPU operating mo...

[Page 67] NEC PD75402A

56 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-11 Processor Clock Control Register Format Note When using a calue of f XX such that 4.19 MHz < fXX ≤ 5.0 MHz, if maximum speed mode : Φ fXX/4 (PCC1, PCC0 = 11) is set as CPU clock frequ...

[Page 68] NEC PD75402A

57 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) System clock oscillation circuit The system clock oscillation circuit oscillates by means of a crystal resonator or ceramic resonator connected to the X1 and X2 pins (standard: 4.194304 MHz). An ext...

[Page 69] NEC PD75402A

58 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-13 Example of Poor Resonator Connection Circuit (2/2) (c) Signal line close to varyin high current (d) Current flows an oscillator power supply line. (potentials at A, B and C fluctuate.) High�...

[Page 70] NEC PD75402A

59 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS ; Assume PCC = 0011. MOV A, #0000 0.95 µ s/4.19 MHz MOV PCC, A ; PCC ← 0000 BR 16 machine cycles 15.3 µ s/4.19 MHz 5.2.3 CPU Clock Setting The CPU clock Φ is the clock supplied to the µ PD754...

[Page 71] NEC PD75402A

60 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS As the PCC is set in 0 by RESET input, Φ is reset-started at the slowest speed (state in which the operating voltage range is wide). For this reason, in a system with a slow supply voltage rise (suc...

[Page 72] NEC PD75402A

61 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.2.4 Differences Between µ PD75402A and µ PD75402 Part of the clock generation circuit differs between the µ PD75402A and the µ PD75402. The µ PD75402 does not include the sections enclosed i...

[Page 73] NEC PD75402A

62 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Next, the processor clock control register (PCC) of the µ PD75402 is shown below. Setting of bit 1 of the PCC is performed by a 4-bit memory handling instruction. At this time, ensure that bits 3, 2 a...

[Page 74] NEC PD75402A

63 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to supply clock pulses to peripheral LSIs, etc. 5.3.1 Clock Output Circuit Configuration The conf...

[Page 75] NEC PD75402A

64 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3.2 Clock Output Mode Register (CLOM) CLOM is a 4-bit register used to control clock output. CLOM is set by a 4-bit memory handling instruction. Bit handling instructions cannot be used. Also, this re...

[Page 76] NEC PD75402A

65 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.3.3 Clock Output Procedure Clock pulse output is performed by the following procedure. (i) Set the clock output mode register. (ii) Write 0 to the P22 output latch. (iii) Set the port 2 input/output m...

[Page 77] NEC PD75402A

66 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4 BASIC INTERVAL TIMER The µ PD75402A is equipped with an 8-bit basic interval timer which has the following functions: (a) Standard time generation (2 different time intervals) (b) Reading counter...

[Page 78] NEC PD75402A

67 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.2 Basic Intercal Timer Mode Register (BTM) BTM is a 4-bit register which controls the operation of the basic interval timer. BTM is set by a 4-bit memory handling instruction. Bit operations are not...

[Page 79] NEC PD75402A

68 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.3 Basic Interval Timer Operation The basic interval timer (BT) is constantly incremented by the clock from the clock generation circuit, and sets the interrupt request flag (IRQBT) when it overflows...

[Page 80] NEC PD75402A

69 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.4.4 Examples of Basic Interval Timer Applications Example 1. In this example the basic interval timer is enabled, and the interrupt generation interval is set to 1.95 ms (at 4.19 MHz operation). SEL ...

[Page 81] NEC PD75402A

70 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.5 SERIAL INTERFACE 5.5.1 Serial Interface Functions The µ PD75402A incorporates a clocked 8-bit serial interface, with the following three modes available. (1) Operation-halted mode This mode is use...

[Page 82] NEC PD75402A

71 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) SBI mode (serial bus interface mode) In the SBI mode, communication is performed with multiple devices by means of two lines: The serial clock (SCK) and the serial data bus (SB0). This mode conforms...

[Page 83] NEC PD75402A

72 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-24 Serial Interface Block Diagram   Internal Bus 8 88 Bit Test CSIM P03/SI P02/SO/SB0 P01/SCK Slave Address  Register (SVA)  Address Comparator Sh...

[Page 84] NEC PD75402A

73 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (1) Serial operating mode register (CSIM) CSIM is an 8-bit register which specifies the serial interface operating mode, serial clock, wake-up function, etc. (See 5.5.3 (1) “Serial operating mode regi...

[Page 85] NEC PD75402A

74 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (8) INTCSI control circuit Controls the generation of interrupt requests. In the following case, the interrupt requests (INTCSI) are generated and interrupt request flags (IRQCSI) are set (see Fig. 6-1 ...

[Page 86] NEC PD75402A

75 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-25 Serial Operating Mode Register (CSIM) Format (1/2) Address 7 6 5 4 3 2 1 0 Symbol FE0H CSIE COI WUP 0 CSIM3 0 CSIM1 0 CSIM Serial Clock Selection Bit (W) Serial Interface Operating Mode Selec...

[Page 87] NEC PD75402A

76 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Note If WUP = 1 is set during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is output after the BUSY release directive until the next fall of the serial clock (SCK). When setti...

[Page 88] NEC PD75402A

77 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Remarks 1. The operating mode can be selected according to the setting of CSIE and CSIM3. CSIE CSIM3 Operating Mode 0 × Operation-halted mode 1 0 3-wire serial I/O mode 1 1 SBI mode 2. The P10/SCK pin ...

[Page 89] NEC PD75402A

78 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) Serial bus interface control register (SBIC) The format of the serial bus interface control register (SBIC) is shown in Fig. 5-26. SBIC is an 8-bit register composed of bits which control the serial...

[Page 90] NEC PD75402A

79 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (2/3) Bus release trigger bit (W) RELT The bus release signal (REL) trigger output control bit. The SO latch is set (1) by setting this bit...

[Page 91] NEC PD75402A

80 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (3/3) Acknowledge enable bit (R/W) ACKE When set before end of transfer ACK is output is synchronization with the 9th SCK clock cycle. When...

[Page 92] NEC PD75402A

81 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Shift register (SIO) The configuration around the shift register is shown in Fig. 5-27. SIO is an 8-bit register which carries out parallel- to-serial conversion and performs serial transmission/rec...

[Page 93] NEC PD75402A

82 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (4) Slave address register (SVA) SVA is an 8-bit register used by the slave to set the slave address value (its own specification number). SVA is a write-only register which is manipulated by 8-bit mani...

[Page 94] NEC PD75402A

83 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS 5.5.4 Operation-Halted Mode The operation-halted mode is used when no serial transfer is performed, allowing power dissipation to be reduced. In this mode, the shift register does not perform shift oper...

[Page 95] NEC PD75402A

84 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Serial clock selection bit (W) The P01/SCK pin status depends on the CSIM1 setting as shown below. CSIM1 P01/SCK Pin Status 0 High impedance 1 High level The following procedure should be used to clear ...

[Page 96] NEC PD75402A

85 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (a) Serial operating mode register (CSIM) When the 3-wire serial I/O mode is used, CSIM is set as shown below (see 5.5.3 (1) “Serial operating mode register” for full details of CSIM). CSIM is manip...

[Page 97] NEC PD75402A

86 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS Signal from address comparator (R) Clearing Conditions (COI = 0) Setting Condition (COI = 1) When slave address register (SVA) and shift register data do not match. COI* When slave address register (SVA...

[Page 98] NEC PD75402A

87 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) When the 3-wire serial I/O mode is used, SBIC is set as shown below (see 5.5.3 (2) “Serial bus interface control register” for full details of SBIC)....

[Page 99] NEC PD75402A

88 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (2) Communication operation In the 3-wire serial I/O mode, data transmission/ reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Shi...

[Page 100] NEC PD75402A

89 CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS (3) Serial clock selection Serial clock selection is performed by setting bit 1 of the serial operating mode register (CSIM). Either of the following clocks can be selected. Table 5-6 Serial Clock Sele...