Silicon Storage SST65P542R User Manual

[Page 1] Silicon Storage SST65P542R

©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SoftPartition is a trademark of Silicon Storage Technology, Inc. These specifications are subject t...

[Page 2] Silicon Storage SST65P542R

2 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 TABLE OF CONTENTS 1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

[Page 3] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 3 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 10.0 THE CORE TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

[Page 4] Silicon Storage SST65P542R

4 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 1.0 INTRODUCTION The SST65P542R is a member of SST’s 8-bit, application-specific microcontroller family targeting IR remote con- troller applicatio...

[Page 5] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 5 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 2.0 BLOCK DIAGRAM IRQ# SuperFlash EEPROM 16K x8 Interrupt Control MCU Core RAM 352K x8 Port A Port B Timer/Counter Interrupt IRO Carrier Modulator ...

[Page 6] Silicon Storage SST65P542R

6 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 3.0 PIN ASSIGNMENTS FIGURE 3-1: PIN ASSIGNMENTS FOR 28-PIN SOIC TABLE 3-1: P IN DESCRIPTIONS Pins Symbol Type 1 1. I = Input O = Output Name and Func...

[Page 7] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 7 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 4.0 MEMORY ORGANIZATION The SST65P542R has a total of 64 KByte of addressable memory. A memory map is shown in Figure 4-1. The memory consists of 32 ...

[Page 8] Silicon Storage SST65P542R

8 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 5.0 MCU CORE AND INSTRUCTION SET This section provides a description of the MCU core registers, the instruction set and the addressing modes. 5.1 Reg...

[Page 9] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 9 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 FIGURE 5-2: STACKING ORDER Stacking decreases memory address and unstacking (Return) increases memory address. 5.1.1 Accumulator (A) The accumulator ...

[Page 10] Silicon Storage SST65P542R

10 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 5.1.5 Processor Status Word (PSW) The PSW is a 5-bit register. These bits can be individually tested by a program, and specific actions can be taken...

[Page 11] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 11 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 5.2.3 Direct (DIR) In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Dir...

[Page 12] Silicon Storage SST65P542R

12 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 5.2.8 Relative (REL) The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte...

[Page 13] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 13 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 5.3 Instruction Set Table 5-1 summarizes the MCU instruction set. A description of the instructions and an explanation of abbrevia- tions follows th...

[Page 14] Silicon Storage SST65P542R

14 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 BHS Branch if higher or same Branch if accumulator is higher or same as memory (C = 0) REL 24 3 2 – – – – – BIH Branch if interrupt line i...

[Page 15] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 15 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 CMP Arithmetic compare memory and accumulator (unsigned) A - M IMM DIR EXT IX IX1 IX2 A1 B1 C1 F1 E1 D1 2 3 4 3 4 5 2 2 3 1 2 3 – – N Z C COM Co...

[Page 16] Silicon Storage SST65P542R

16 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 LDA Load accumulator with memory M → A IMM DIR EXT IX IX1 IX2 A6 B6 C6 F6 E6 D6 2 3 4 3 4 5 2 2 3 1 2 3 – – N Z – LDX Load index X with memo...

[Page 17] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 17 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 RTS Return from subroutine PC ↑ ; PC + 1 → PC INH 81 6 1 – – – – – SBC Subtract memory from accumulator with borrow A-M-C → A IMM DI...

[Page 18] Silicon Storage SST65P542R

18 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 Description The following is the description of each instruction and the operation during the execution of each instruction. The key for MCU instruc...

[Page 19] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 19 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 6.0 I/O REGISTERS DEFINITION The 32 Bytes of I/O registers occupy address locations from 0000H to 001FH and include general purpose I/O pin register...

[Page 20] Silicon Storage SST65P542R

20 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 TABLE 6-2: BIT DEFINITIONS OF I/O REGISTERS (1 OF 2) Addr Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0000H Port A Data Register PA7 PA6 ...

[Page 21] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 21 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 Please see Section 10.0 for Core Timer and Section 11.0 for CMT register definitions. All other register definitions are described in detail in the ...

[Page 22] Silicon Storage SST65P542R

22 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 7.0 INTERRUPTS The MCU has 6 sources of interrupts including reset, a software interrupt and 4 hardware interrupt lines. If more than one interrupt ...

[Page 23] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 23 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 8.0 RESETS AND CLOCKS SST65P542R has two sources for external reset: LPRST# and RESET#. After LPRSET# switches from low to high, 4064 clock cycles a...

[Page 24] Silicon Storage SST65P542R

24 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 9.0 POWER-DOWN MODES SST65P542R offers two modes to reduce system power consumption. 9.1 STOP Mode To enter the STOP Mode, write 01H to the Power Sa...

[Page 25] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 25 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 10.0 THE CORE TIMER The core timer is a 14-stage, multifunctional ripple counter. Its features include Timer Overflow (TO), Power-On Reset (POR), Re...

[Page 26] Silicon Storage SST65P542R

26 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 10.1 Computer Operating Properly Watchdog Timer Control Register (CWTC) Writing to CWT Control register (000DH) can enable/disable core timer. 10.2...

[Page 27] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 27 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 10.2.7 Real-Time Interrupt Rate Select (RT1-RT0) These two bits select any one-of-four taps from the real-time interrupt circuit stages. Please refe...

[Page 28] Silicon Storage SST65P542R

28 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 11.0 CARRIER MODULATOR TRANSMITTER (CMT) The carrier modulator transmitter (CMT) module is tailored for the IR remote controller applications. This ...

[Page 29] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 29 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 To enable carrier generator clocks, the MCGEN bit in the MCSR must be set and the BASE bit in the MCSR must be cleared. The block diagram is shown b...

[Page 30] Silicon Storage SST65P542R

30 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 11.1.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2) There are two sets of Carrier Generator Data Registers: Primary and secondary. ...

[Page 31] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 31 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 time values are undefined out of reset. These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious resu...

[Page 32] Silicon Storage SST65P542R

32 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 Here are the equations to calculate mark and space period for time mode: Setting the DIV2 bit in the BCSR will double mark and space times. FIGURE 1...

[Page 33] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 33 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 11.2.3 Extended Space Operation In either time or FSK mode, the space period can be made longer than the maximum possible value of SBUFF. Set- ting ...

[Page 34] Silicon Storage SST65P542R

34 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 DIV2 Divide-by-two prescaler Setting this bit to 1 causes the modulator output to be timed at a twice-slower clock, i.e., doubled the mark and spac...

[Page 35] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 35 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 11.2.5 Modulator Period Data Register (MDR1, MDR2, and MDR3) The MBUFF and SBUFF are 12-bit registers and can be accessed through three 8-bit regist...

[Page 36] Silicon Storage SST65P542R

36 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 12.0 PROGRAMMING FLOW DIAGRAM FIGURE 12-1: IN-APPLICATION PROGRAMMING FIGURE 12-2: IN-APPLICATION ERASE 4004 F16.2 Write 88H to address 0BH Write da...

[Page 37] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 37 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 FIGURE 12-3: EXTERNAL FLASH BYTE-PROGRAM ALGORITHM FOR EXTERNAL FLASH PROGRAMMING MODE Note: Please refer to the SST65P542R data sheet for more info...

[Page 38] Silicon Storage SST65P542R

38 SST65P542R Programming Reference Manual ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 FIGURE 12-4: CHIP-/SECTOR-ERASE COMMAND SEQUENCE FOR EXTERNAL FLASH PROGRAMMING MODE Note: Please refer to the SST65P542R data sheet for more inform...

[Page 39] Silicon Storage SST65P542R

SST65P542R Programming Reference Manual 39 ©2003 Silicon Storage Technology, Inc. S74004-00-000 4/03 13.0 PACKAGING DIAGRAMS 28-PIN SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) SST P ACKAGE CODE: SG 28-soic-SG-5 Note: 1. Complies with JEDEC publication...